ALDEC DEMO - HDL Linting for RISC V Cores

The entire processor industry is currently going through a paradigm shift - new generations of domain-specific proprietary processor cores based on the open-source RISC-V ISA are now being developed by various industry-leading semiconductor companies. Additionally, open-source RISC-V processor cores such as SweRV, Ibex and Pulp are now available, and they are actively being developed in various open-source Github communities. Static verification or linting is a standard part of the tool flow for any process