2.1 - Active HDL™ (v13.1) Design Entry: Block Diagram Editor

The Block Diagram Editor is a tool for graphical entry of VHDL, Verilog and EDIF designs. If your HDL design is in large part structural, it may be easier for you to enter its description graphically as a block diagram, rather than typing hundreds of source code lines. The Block Diagram Editor will then convert the diagram automatically into structural VHDL, Verilog or EDIF netlist. With Active-HDL, you can mix different types of description. In this video we will take a close look at some essential block diagram editor features that will help you design your BDE file much more easily and smoothly.